Datasheet

Datasheet, Volume 2 75
Processor Configuration Registers
2.8.10 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG Register
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 250-251h
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:11 RO 00h Reserved
10:6 RW 00h
Write To Precharge Delay (C0sd_cr_wr_pchg)
This field indicates the minimum allowed spacing (in DRAM clocks) between
the WRITE and PRE commands to the same rank-bank.
This value corresponds to the tWR parameter in the DDR3 Specification.
5:2 RW 0h
Read To Precharge Delay (C0sd_cr_rd_pchg)
This field indicates the minimum allowed spacing (in DRAM clocks) between
the READ and PRE commands to the same rank-bank.
1:0 RW 00b
Precharge To Precharge Delay (C0sd_cr_pchg_pchg)
This configuration register indicates the minimum allowed spacing (in DRAM
clocks) between two PRE commands to the same rank.