Datasheet

Processor Configuration Registers

72 Datasheet, Volume 2

2.8.6 C0DRB3—Channel 0 DRAM Rank Boundary Address 3

See C0DRB0 register description for details.

B/D/F/Type: 0/0/0/MCHBAR

Address Offset: 206–207h

Reset Value: 0000h

Access: RO, RW-L

Bit Attr

Reset

Value

Description

15:10 RO 00h Reserved

9:0 RW-L 000h

Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3)

This register defines the DRAM rank boundary for rank3 of Channel 0 (64 MB

granularity)

=(R3 + R2 + R1 + R0)

R0 = Total rank0 memory size/64 MB

R1 = Total rank1 memory size/64 MB

R2 = Total rank2 memory size/64 MB

R3 = Total rank3 memory size/64 MB

This register is locked by Memory pre-allocated for MR lock.