Datasheet

Datasheet, Volume 2 71
Processor Configuration Registers
2.8.4 C0DRB1—Channel 0 DRAM Rank Boundary Address 1
Register
See C0DRB0 register description for details.
2.8.5 C0DRB2—Channel 0 DRAM Rank Boundary Address 2
Register
See C0DRB0 register description for details.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 202–203h
Reset Value: 0000h
Access: RW-L, RO
Bit Attr
Reset
Value
Description
15:10 RO 00h Reserved
9:0 RW-L 000h
Channel 0 DRAM Rank Boundary Address 1 (C0DRBA1)
This register defines the DRAM rank boundary for rank1 of Channel 0 (64 MB
granularity)
=(R1 + R0)
R0 = Total rank0 memory size/64 MB
R1 = Total rank1 memory size/64 MB
R2 = Total rank2 memory size/64 MB
R3 = Total rank3 memory size/64 MB
This register is locked by Memory pre-allocated for ME lock.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 204–205h
Reset Value: 0000h
Access: RO, RW-L
Bit Attr
Reset
Value
Description
15:10 RO 00h Reserved
9:0 RW-L 000h
Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2)
This register defines the DRAM rank boundary for rank2 of Channel 0 (64 MB
granularity)
=(R2 + R1 + R0)
R0 = Total rank0 memory size/64 MB
R1 = Total rank1 memory size/64 MB
R2 = Total rank2 memory size/64 MB
R3 = Total rank3 memory size/64 MB
This register is locked by Memory pre-allocated for ME lock.