Datasheet

Processor Configuration Registers
68 Datasheet, Volume 2
2.8.1 CSZMAP—Channel Size Mapping Register
This register indicates the total memory that is mapped to Interleaved and Asymmetric
operation respectively (1 MB granularity) used for Channel address decode.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 100–107h
Reset Value: 0000_0000_0000_0000h
Access: RW
Bit Attr
Reset
Value
Description
63:48 RO 0h Reserved
47:32 RW-L 0000h
2 Channel Size (2CHSZ)
This register indicates the total memory that is mapped to 2-channel
operation (1 MB granularity)
This register is locked by ME pre-allocated Memory lock and may also be
forced to 0000h by the Performance Dual Channel Disable fuse.
31:16 RW-L 0000h
1 Channel Size (1CHSZ)
This register indicates the total memory that is mapped to 1-channel
operation (1 MB granularity)
This register is locked by ME pre-allocated Memory lock.
15:0 RW-L 0000h
Channel 0 Single Channel Size (C0SCSIZE)
This register indicates the quantity of memory physically in channel 0 that is
mapped to 1-channel operation (1 MB granularity).