Datasheet

Processor Configuration Registers
62 Datasheet, Volume 2
2.7.24 ERRSTS—Error Status Register
This register is used to report various error conditions using the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit, by software writing a 1 to it.
B/D/F/Type: 0/0/0/PCI
Address Offset: C8–C9h
Reset Value: 0000h
Access: RO, RW1C-S
BIOS Optimal Reset Value 0h
Bit Attr
Reset
Value
Description
15:13 RO 000b Reserved
12 RW1C-S 0b
Processor Software Generated Event for SMI (GSGESMI)
This bit indicates the source of the SMI was a Device 2 Software Event.
11 RW1C-S 0b
Processor Thermal Sensor Event for SMI/SCI/SERR (GTSE)
This bit indicates that a processor Thermal Sensor trip has occurred and an
SMI, SCI or SERR has been generated. The status bit is set only if a message
is sent based on thermal event enables in Error command, SMI command
and SCI command registers. A trip point can generate one of SMI, SCI, or
SERR interrupts (two or more per event is illegal). Multiple trip points can
generate the same interrupt, if software chooses this mode, subsequent
trips may be lost. If this bit is already set, then an interrupt message will not
be sent on a new thermal sensor event.
10 RO 0b Reserved
9RW1C-S 0b
LOCK to non-DRAM Memory Flag (LCKF)
When this bit is set to 1, the processor has detected a lock operation to
memory space that did not map into DRAM.
8:2 RO 0b Reserved
1RW1C-S 0bReserved
0RW1C-S 0bReserved