Datasheet

Processor Configuration Registers
60 Datasheet, Volume 2
2.7.21 TOLUD—Top of Low Usable DRAM Register
This 16-bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics memory,
and Memory pre-allocated for graphics are within the usable DRAM space defined.
Programming Example:
C1DRB3 is set to 5 GB
BIOS knows the OS requires 1 GB of PCI space.
BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable by the
system. This 20 MB range at the very top of addressable memory space is lost to APIC
and Intel TXT.
According to the above information, TOLUD is originally calculated to:
4 GB = 1_0000_0000h
The system memory requirements are: 4 GB – 1 GB (PCI space) – 20 MB (lost
memory)
Due to the minimum granularity of the REMAPBASE and REMAPLIMIT registers, this
becomes 3 GB – 64 MB = 0_BC00_0000h
Since 0_BC00_0000h (PCI and other system requirements) is less than
1_0000_0000h, TOLUD should be programmed to BC0h.
These bits are Intel TXT lockable.
B/D/F/Type: 0/0/0/PCI
Address Offset: B0–B1h
Reset Value: 0010h
Access: RW-L, RO
Bit Attr
Reset
Value
Description
15:4 RW-L 001h
Top of Low Usable DRAM (TOLUD)
This register contains bits 31:20 of an address one byte above the maximum
DRAM memory below 4 GB that is usable by the operating system. Address
bits 31:20 programmed to 01h implies a minimum memory size of 1 MB.
Configuration software must set this value to the smaller of the following 2
choices: maximum amount memory in the system minus memory pre-
allocated for ME plus one byte or the minimum address allocated for PCI
memory.
Address bits 19:0 are assumed to be 0_0000h for the purposes of address
comparison. The Host interface positively decodes an address towards DRAM
if the incoming address is less than the value programmed in this register.
The Top of Low Usable DRAM is the lowest address above both memory pr-
allocated for graphics and TSEG. BIOS determines the base of memory pre-
allocated for graphics by subtracting the memory pre-allocated for Graphics
Size from TOLUD and further decrements by TSEG size to determine the base
of TSEG. All the bits in this register are locked in Intel TXT mode.
This register must be 64 MB aligned when reclaim is enabled.
3:0 RO 0h Reserved