Datasheet
Datasheet, Volume 2 55
Processor Configuration Registers
2.7.15 DMIBAR—Root Complex Register Range Base Address
Register
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the processor. There is no physical memory within this 4 KB window
that can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. On reset, the Root Complex configuration space is
disabled and must be enabled by writing a 1 to DMIBAREN [Device 0, offset 68h, bit 0].
All the bits in this register are locked in Intel TXT mode.
B/D/F/Type: 0/0/0/PCI0000_0
Address Offset: 68–6Fh
Reset Value: 0000_0000_0000_0000h
Access: RW-L, RO
Bit Attr
Reset
Value
Description
63:36 RO 0000000h Reserved (DMIBAR_rsv)
35:12 RW-L 000000h
DMI Base Address (DMIBAR)
This field corresponds to bits 35:12 of the base address DMI configuration
space. BIOS will program this register resulting in a base address for a 4 KB
block of contiguous memory address space. This register ensures that a
naturally aligned 4 KB space is allocated within the first 64 GB of addressable
memory space. System software uses this base address to program the DMI
register set. All the bits in this register are locked in Intel TXT mode.
11:1 RO 000h Reserved
0RW-L 0b
DMIBAR Enable (DMIBAREN)
0 = Disable. DMIBAR is disabled and does not claim any memory
1 = Enable. DMIBAR memory mapped accesses are claimed and decoded
appropriately
This register is locked by Intel TXT.