Datasheet

Datasheet, Volume 2 51
Processor Configuration Registers
2.7.10 SID—Subsystem Identification Register
This value is used to identify a particular subsystem.
2.7.11 PXPEPBAR—PCI Express Egress Port Base Address
Register
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4 KB window that can be addressed. The 4 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the EGRESS port MMIO configuration space is disabled and must be
enabled by writing a 1 to PXPEPBAREN [Device 0, offset 40h, bit 0].
All the bits in this register are locked in Intel TXT mode.
B/D/F/Type: 0/0/0/PCI
Address Offset: 2E–2Fh
Reset Value: 0000h
Access: RW-O
Bit Attr
Reset
Value
Description
15:0 RW-O 0000h
Subsystem ID (SUBID)
This field should be programmed during BIOS initialization. After it has been
written once, it becomes read only.
B/D/F/Type: 0/0/0/PCI
Address Offset: 40–47h
Reset Value: 0000_0000_0000_0000h
Access: RW-L, RO
Bit Attr
Reset
Value
Description
63:36 RO 0000000h Reserved
35:12 RW-L 000000h
PCI Express Egress Port MMIO Base Address (PXPEPBAR)
This field corresponds to bits 35:12 of the base address PCI Express Egress
Port MMIO configuration space. BIOS will program this register resulting in a
base address for a 4 KB block of contiguous memory address space. This
register ensures that a naturally aligned 4 KB space is allocated within the
first 64 GB of addressable memory space. System Software uses this base
address to program the processor MMIO register set. All the bits in this
register are locked in Intel TXT mode.
11:1 RO 000h Reserved
0RW-L 0b
PXPEPBAR Enable (PXPEPBAREN)
0 = Disable. PXPEPBAR is disabled and does not claim any memory
1 = Enable. PXPEPBAR memory mapped accesses are claimed and decoded
appropriately
This register is locked by Intel TXT.