Datasheet

Datasheet, Volume 2 47
Processor Configuration Registers
2.7.3 PCICMD—PCI Command Register
Since processor Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
B/D/F/Type: 0/0/0/PCI
Address Offset: 4–5h
Reset Value: 0006h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:10 RO 00h Reserved
9RO 0b
Fast Back-to-Back Enable (FB2B)
This bit controls whether or not the master can do fast back-to-back write.
Since device 0 is strictly a target this bit is not implemented and is hardwired
to 0. Writes to this bit position have no effect.
8RW 0b
SERR Enable (SERRE)
This bit is a global enable bit for Device 0 SERR messaging. The processor
does not have an SERR signal. The processor communicates the SERR
condition by sending an SERR message over DMI to the PCH.
1 = The processor is enabled to generate SERR messages over DMI for
specific Device 0 error conditions that are individually enabled in the
ERRCMD and DMIUEMSK registers. The error status is reported in the
ERRSTS, PCISTS, and DMIUEST registers.
0 = The SERR message is not generated by the processor for Device 0.
This bit only controls SERR messaging for Device 0. Device 1 has its own
SERRE bits to control error reporting for error conditions occurring in that
device. The control bits are used in a logical OR manner to enable the SERR
DMI message mechanism.
0 = Device 0 SERR disabled
1 = Device 0 SERR enabled
7RO 0b
Address/Data Stepping Enable (ADSTEP)
Address/data stepping is not implemented in the processor, and this bit is
hardwired to 0. Writes to this bit position have no effect.
6RW 0b
Parity Error Enable (PERRE)
This bit controls whether or not the Master Data Parity Error bit in the PCI
Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
5RO 0b
VGA Palette Snoop Enable (VGASNOOP)
The processor does not implement this bit and it is hardwired to a 0. Writes
to this bit position have no effect.
4RO 0b
Memory Write and Invalidate Enable (MWIE)
The processor will never issue memory write and invalidate commands. This
bit is therefore hardwired to 0. Writes to this bit position will have no effect.
3:3 RO 0h Reserved
2RO 1b
Bus Master Enable (BME)
The processor is always enabled as a master on the backbone. This bit is
hardwired to a 1. Writes to this bit position have no effect.
1RO 1b
Memory Access Enable (MAE)
The processor always allows access to main memory, except when such
access would violate security principles. Such exceptions are outside the
scope of PCI control. This bit is not implemented and is hardwired to 1.
Writes to this bit position have no effect.
0RO 0b
I/O Access Enable (IOAE)
This bit is not implemented in the processor and is hardwired to a 0. Writes
to this bit position have no effect.