Datasheet

Datasheet, Volume 2 45
Processor Configuration Registers
2.7 PCI Express* Device 0 Registers
Table 2-4 shows the PCI Express Device 0 register address map. Detailed register bit
descriptions follow Table 2-4.
Table 2-4. PCI Express* Device 0 Register Address Map
Offset
Address
Register
Symbol
Register Name Reset Value Access
0–1h VID Vendor Identification 8086h RO
2–3h DID Device Identification 0040h RO
4–5h PCICMD PCI Command 0006h RO, RW
6–7h PCISTS PCI Status 0090h RW1C, RO
8h RID Revision Identification 12h RO
9–Bh CC Class Code 060000h RO
Dh MLT Master Latency Timer 00h RO
Eh HDR Header Type 00h RO
2C–2Dh SVID Subsystem Vendor Identification 0000h RW-O
2E–2Fh SID Subsystem Identification 0000h RW-O
40–47h PXPEPBAR
PCI Express Egress Port Base Address 0000_0000_0
000_0000h
RW-L, RO
48–4Fh MCHBAR
MCH Memory Mapped Register Range Base 0000_0000_0
000_0000h
RW-L, RO
52–53h GGC Graphics Control Register 0030h RW-L, RO
54–57h DEVEN Device Enable 0000210Bh RW-L, RO
68–6Fh DMIBAR
Root Complex Register Range Base Address 0000_0000_0
000_0000h
RW-L, RO
97h LAC Legacy Access Control 00h RW
A2–A3h TOUUD Top of Upper Usable DRAM 0000h RW-L
A4–A7h GBSM Graphics Base of Pre-Allocated Memory 0000_0000h RW-L, RO
A8–ABh BGSM Base of GTT Pre-allocated memory 0000_0000h RW-L, RO
AC–AFh TSEGMB TSEG Memory Base 0000_0000h RO, RW-L
B0–B1h TOLUD Top of Low Usable DRAM 0010h RW-L, RO
C0–C3h PBFC Primary Buffer Flush Control 0000_0000h RO, W
C4–C7h SBFC Secondary Buffer Flush Control 0000_0000h RO, W
C8–C9h ERRSTS Error Status 0000h RO, RW1C-S
CA–CBh ERRCMD Error Command 0000h RO, RW
DC–DFh SKPD Scratchpad Data 0000_0000h RW
E0–EBh CAPID0
Capability Identifier SKU
dependent
RO
F4h MCSAMPML
Memory Configuration, System Address Map
and Pre-allocated Memory Lock
00h
RW-O, RW-L,
RW-L-K