Datasheet

Datasheet, Volume 2 43
Processor Configuration Registers
2.4.5.2 DMI Configuration Accesses
Accesses to disabled processor internal devices, bus numbers not claimed by the Host-
PCI Express bridge, or PCI Bus 0 devices not part of the processor will subtractively
decode to the PCH and consequently be forwarded over the DMI using a PCI Express
configuration TLP.
If the Bus Number is zero, the processor will generate a Type 0 Configuration cycle TLP
on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the
Host-PCI Express bridge, the processor will generate a Type 1 Configuration cycle TLP
on DMI.
The PCH routes configurations accesses in a manner similar to the processor. The PCH
decodes the configuration TLP and generates a corresponding configuration access.
Accesses targeting a device on PCI Bus 0 may be claimed by an internal device. The
PCH compares the non-zero Bus Number with the Secondary Bus Number and
Subordinate Bus Number registers of its PCI-to-PCI bridges to determine if the
configuration access is meant for Primary PCI, or some other downstream PCI bus or
PCI Express link.
Configuration accesses that are forwarded to the PCH, but remain unclaimed by any
device or bridge will result in a master abort.
2.5 Processor Register Introduction
The processor contains two sets of software accessible registers, accessed using the
Host processor I/O address space — Control registers and internal configuration
registers.
• Control registers are I/O mapped into the processor I/O space, which control
access to PCI and PCI Express configuration space (see section entitled I/O Mapped
Registers).
• Internal configuration registers residing within the processor are partitioned into
three logical device register sets (“logical” since they reside within a single physical
device). The first register set is dedicated to Host Bridge functionality (that is,
DRAM configuration, other chip-set operating parameters and optional features).
The second register block is dedicated to Host-PCI Express Bridge functions
(controls PCI Express interface configurations and operating parameters). The third
register block is for the internal graphics functions.
The processor internal registers (I/O Mapped, Configuration and PCI Express Extended
Configuration registers) are accessible by the Host processor. The registers that reside
within the lower 256 bytes of each device can be accessed as Byte, Word (16 bit), or
DWord (32 bit) quantities, with the exception of CONFIG_ADDRESS, which can only be
accessed as a DWord. All multi-byte numeric fields use "little-endian" ordering (that is,
lower addresses contain the least significant parts of the field). Registers that reside in
bytes 256 through 4095 of each device may only be accessed using memory mapped
transactions in DWord (32 bit) quantities.
Some of the processor registers described in this section contain reserved bits. These
bits are labeled "Reserved”. Software must deal correctly with fields that are reserved.
On reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit