Datasheet

Datasheet, Volume 2 41
Processor Configuration Registers
2.4.4 Internal Device Configuration Accesses
The processor decodes the Bus Number (Bits 23:16) and the Device Number fields of
the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a PCI Bus 0 device.
If the targeted PCI Bus 0 device exists in the processor and is not disabled, the
configuration cycle is claimed by the appropriate device.
Figure 2-10. Processor Configuration Cycle Flow Chart
DW I/O Write to
CONFIG_ADDRESS
with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
Processor Generates
Type 1 Access
to PCI Express
Processor allows
cycle to go to DMI
resulting in Master
Abort
Bus# > SEC BUS
Bus#  SUB BUS
in Bus 0
Dev 1
Bus# = 0
Device# = 0 &
Function# = 0
Processor Generates
DMI Type 1
Configuration Cycle
Bus# =
SECONDARY BUS
in Bus 0
Dev 1
Processor
Claims
Yes
No
Yes
Yes
No
No
Yes
No
No
Device# = 0
Processor Generates
Type 0 Access
to PCI Express
Yes
Processor Generates
DMI Type0
Configuration Cycles
Device # = 1 &
Dev # 1 Enabled
& Function# = 0
Processor
Claims
Yes
No
Processor
Claims
Yes
No
Device # = 2 &
Dev # 2 Enabled
& Function# = 0
Dev # 1
Enabled &
Dev # 1
Enabled &