Datasheet

Processor Configuration Registers
40 Datasheet, Volume 2
Just the same as with PCI devices, each device is selected based on decoded address
information that is provided as a part of the address portion of Configuration Request
packets. A PCI Express device will decode all address information fields (bus, device,
function and extended address numbers) to provide access to the correct register.
To access this space (step 1 is done only once by BIOS),
First determine the maximum bus number using the following algorithm.
1. Write to I/O address 0CF8h with value 80FF_1050h.
2. Read from I/O address 0CFCh. If the value is FFFF_FFFFh (master abort), then go
to step 3, otherwise max bus number is FFh.
3. Write to I/O address 0CF8h with value 807F_1050h.
4. Read from I/O address 0CFCh. If the value is FFFF_FFFFh (master abort), then
maximum bus number is 3Fh; otherwise, maximum bus number is 7Fh.
Write to the PCIEXBAR register at the maximum bus number, device 2, function 0,
offset 50h. Write 1 to bit 0 of the register to enable the enhanced configuration
mechanism. Allocate either 256, 128, or 64 busses to PCI Express by writing “000”,
“111”, or “110” respectively to bits 3:1. Pick a naturally aligned base address for
mapping the configuration space onto memory space using 1 MB per bus number and
write that base address into Bits 39:20.
Calculate the host address of the register you wish to set using (PCI Express base +
(bus number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) + (1 B *
offset within the function) = host address)
Use a memory write or memory read cycle to the calculated host address to write or
read that register.
2.4.3 Routing Configuration Accesses
The processor supports two PCI related interfaces — DMI and PCI Express. The
processor is responsible for routing PCI and PCI Express configuration cycles to the
appropriate device that is an integrated part of the processor or to one of these two
interfaces. Configuration cycles to the PCH internal devices and Primary PCI (including
downstream devices) are routed to the PCH using DMI. Configuration cycles to both the
PCI Express Graphics PCI compatibility configuration space and the PCI Express
Graphics extended configuration space are routed to the PCI Express Graphics port
device or associated link.