Datasheet

Datasheet, Volume 2 37
Processor Configuration Registers
Note that the processor Device 1 I/O address range registers defined above are used
for all I/O space allocation for any devices requiring such a window on PCI-Express.
The PCICMD1 register can disable the routing of I/O cycles to PCI-Express.
2.3 Configuration Process and Registers
2.3.1 Platform Configuration Structure
The DMI physically connects the processor and the Intel PCH; so, from a configuration
standpoint, the DMI is logically PCI Bus 0. As a result, all devices internal to the
processor and the Intel PCH appear to be on PCI Bus 0.
Note: The PCH internal LAN controller does not appear on Bus 0 — it appears on the external
PCI bus (whose number is configurable).
The system’s primary PCI expansion bus is physically attached to the PCH and, from a
configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI
bridge and therefore has a programmable PCI Bus number. The PCI Express Graphics
Attach appears to system software to be a real PCI bus behind a PCI-to-PCI bridge that
is a device resident on PCI Bus 0.
Note: A physical PCI bus 0 does not exist. DMI and the internal devices in the processor and
PCH logically constitute PCI Bus 0 to configuration software.
The processor contains the following PCI devices within a single physical component.
The configuration registers for these devices are mapped as devices residing on PCI
Bus 0.
Device 0 — Host Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI Bus 0. Device 0 contains the standard PCI header registers, PCI
Express base address register, DRAM control (including thermal/throttling control),
configuration for the DMI, and other processor specific registers.
Device 1 — Host-PCI Express Bridge. Logically this appears as a “virtual” PCI-to-
PCI bridge residing on PCI Bus 0 and is compliant with PCI Express Base
Specification. Device 1 contains the standard PCI-to-PCI bridge registers and the
standard PCI Express/PCI configuration registers (including the PCI Express
memory address mapping).
Device 2 — Internal Graphics Device. Logically, this appears as an APCI device
residing on PCI Bus 0. Physically, Device 2 contains the configurations registers for
3D, 2D, and display functions.
Device 6 Secondary Host to PCI Express Bridge. (Not supported on all SKUs)