Datasheet

Intel
®
QuickPath Architecture System Address Decode Register Description
358 Datasheet, Volume 2
3.8.2 QPI_0_PH_CTR, QPI_1_PH_CTR
This is the Intel QPI Physical Layer Control Register.
Device: 2
Function: 1
Offset: 6Ch
Access as a Dword
Bit Type
Reset
Value
Description
31:28 RV 0 Reserved
27 RW 0
LA_LOAD_DISABLE
This bit disables the loading of the effective values of the Intel QPI CSRs
when set.
26:24 RV 0 Reserved
23 RW 0
ENABLE_PRBS
This bit enables LFSR pattern during bitlock/training.
1 = Use pattern in bitlock/retraining.
0 = Use clock pattern for bitlock/retraining.
22 RW 0
ENABLE_SCRAMBLE
This bit enables data scrambling through LFSR.
1 = Data scrambled/descrambled with LFSR
0 = Data not scrambled/descrambled.
21:16 RV 0 Reserved
15:14 RW 2
DETERMINISM_MODE. Sets determinism mode of operation.
00 = Non-deterministic initialization.
01 = Slave mode initialization.
10 = Master mode of initialization - valid only if a component can
generate its PhyL0Synch.
13 RW 1
DISABLE_AUTO_COMP. Disables automatic entry into compliance.
0 = Path from detect.clkterm to compliance is allowed.
1 = Path from detect.clkterm to compliance is disabled.
12 RW 0
INIT_FREEZE
When this bit is set, it freezes the FSM when initialization aborts.
11 RW 0
DISABLE_ISI_CHECK
Defeature mode to disable ISI checking during Polling.LaneDeskew state.
10:8 RW 0
INIT_MODE
Initialization mode that determines altered initialization modes.
7RW0
LINK_SPEED. Identifies slow speed or at-speed operation for the Intel
QPI port.
1 = Force direct operational speed initialization.
0 = Slow speed initialization.
6RV0Reserved
5RW1PHYINITBEGIN. Instructs the port to start initialization.
4RW0SINGLE_STEP. Enables single step mode.
3RW0LAT_FIX_CTL. If set, instructs the remote agent to fix the latency.
2RW0
BYPASS_CALIBRATION. Indicates the physical layer to bypass
calibration.
1RW0RESET_MODIFIER. Modifies soft reset to default reset when set.
0RW1S0PHY_RESET. Physical Layer Reset.