Datasheet
Datasheet, Volume 2 35
Processor Configuration Registers
2.2.7 System Management Mode (SMM)
The processor handles all SMM mode transaction routing. The processor has no direct
knowledge of SMM mode. The processor will never allow I/O devices access to
CSEG/TSEG/HSEG ranges.
DMI Interface and PCI Express masters are not allowed to access the SMM space.
2.2.8 SMM and VGA Access through GTT TLB
Accesses through GTT TLB address translation SMM DRAM space are not allowed.
Writes will be routed to Memory address 000C_0000h with byte enables de-asserted
and reads will be routed to Memory address 000C_0000h. If a GTT TLB translated
address hits SMM DRAM space, an error is recorded in the PGTBL_ER register.
PCI Express and DMI Interface originated accesses are never allowed to access SMM
space directly or through the GTT TLB address translation. If a GTT TLB translated
address hits enabled SMM DRAM space, an error is recorded in the PGTBL_ER register.
PCI Express* and DMI Interface write accesses through GMADR range will not be
snooped. Only PCI Express* and DMI assesses to GMADR linear range (defined using
fence registers) are supported. PCI Express and DMI Interface tileY and tileX writes to
GMADR are not supported. If, when translated, the resulting physical address is to
enabled SMM DRAM space, the request will be remapped to address 000C_0000h with
de-asserted byte enables.
PCI Express and DMI Interface read accesses to the GMADR range are not supported;
therefore, will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete with
UR (unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure that they are not in SMM
(actually, anything above base of TSEG or 640 KB–1 MB). Thus, they will be invalid and
go to address 000C_0000h, but that is not specific to PCI Express or DMI; it applies to
the processor or internal graphics engines.
2.2.9 I/O Address Space
The processor generates either DMI Interface or PCI Express* bus cycles for all
processor I/O accesses that it does not claim. The processor no longer contains the two
internal registers in the processor I/O space, Configuration Address Register
(CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA). The
processor now handles accesses to these registers, which ultimate generate a QPI
configuration access.
The processor allows 64K+3 bytes to be addressed within the I/O space. The processor
propagates the processor I/O address without any translation on to the destination bus
and, therefore, provides addressability for 64K+3 byte locations. Note that the upper 3
Table 2-2. SMM Regions
SMM Space Enabled Transaction Address Space DRAM Space (DRAM)
Compatible (C) 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh
TSEG (T) (TOLUD–STOLEN–TSEG) to
TOLUD-STOLEN
(TOLUD–STOLEN–TSEG) to
TOLUD-STOLEN