Datasheet

Intel
®
QuickPath Architecture System Address Decode Register Description
348 Datasheet, Volume 2
4RO0
Capability List (CLIST)
This bit is hard wired to 1 to indicate to the configuration software that
this device/function implements a list of new capabilities. A list of new
capabilities is accessed using registers CAPPTR at the configuration
address offset 34h from the start of the PCI configuration space header of
this function. Register CAPPTR contains the offset pointing to the start
address with configuration space of this device where the capability
register resides. This bit must be set for a PCI Express device or if the
VSEC capability.
If no capability structures are implemented, this bit is hard wired to 0.
3RO0
Interrupt Status
If this device generates an interrupt, then this read-only bit reflects the
state of the interrupt in the device/function. Only when the Interrupt
Disable bit in the command register is a 0 and this Interrupt Status bit is
a 1, will the device’s/function’s INTx# signal be asserted. Setting the
Interrupt Disable bit to a 1 has no effect on the state of this bit.
If this device does not generate interrupts, then this bit is not
implemented (RO and reads returns 0).
2:0 RO 0 Reserved
Device: 0
Function: 0–1
Offset: 06h
Device: 2
Function: 0–1
Offset: 06h
Bit Type
Reset
Value
Description