Datasheet

Datasheet, Volume 2 345
Intel
®
QuickPath Architecture System Address Decode Register Description
3.4.5 HDR—Header Type Register
This register identifies the header layout of the configuration space.
3.4.6 SID/SVID—Subsystem Identity/Subsystem Vendor
Identification Register
This register identifies the manufacturer of the system. This 32-bit register uniquely
identifies any PCI device.
Device: 0
Function: 0–1
Offset: 0Eh
Device: 2
Function: 0–1
Offset: 0Eh
Bit Type
Reset
Value
Description
7RO1
Multi-function Device
This bit selects whether this is a multi-function device, that may have
alternative configuration layouts. This bit is hard wired to 1 for devices in
the processor.
6:0 RO 0
Configuration Layout
This field identifies the format of the configuration header layout for a
PCI-to-PCI bridge from bytes 10h through 3Fh.
For all devices, the default is 00h indicating a conventional type 00h PCI
header.
Device: 0
Function: 0–1
Offset: 2Ch, 2Eh
Device: 2
Function: 0–1
Offset: 2Ch, 2Eh
Access as a DWord
Bit Type
Reset
Value
Description
31:16 RWO 8086h
Subsystem Identification Number
The Reset Value specifies Intel
15:0 RWO 8086h
Vendor Identification Number
The Reset Value specifies Intel.