Datasheet
Datasheet, Volume 2 339
Intel
®
QuickPath Architecture System Address Decode Register Description
Table 3-4. Device 0, Function 1 — System Address Decoder Registers
DID VID 00h SAD_DRAM_RULE_0 80h
PCISTS PCICMD 04h SAD_DRAM_RULE_1 84h
CCR RID 08h SAD_DRAM_RULE_2 88h
HDR 0Ch SAD_DRAM_RULE_3 8Ch
10h SAD_DRAM_RULE_4 90h
14h SAD_DRAM_RULE_5 94h
18h SAD_DRAM_RULE_6 98h
1Ch SAD_DRAM_RULE_7 9Ch
20h
A0h
24h
A4h
28h
A8h
SID SVID 2Ch
ACh
30h
B0h
34h
B4h
38h
B8h
3Ch
BCh
SAD_PAM0123 40h
C0h
SAD_PAM456 44h
C4h
SAD_HEN 48h
C8h
SAD_SMRAM 4Ch
CCh
SAD_PCIEXBAR
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch ECh
70h F0h
74h F4h
78h F8h
7Ch FCh