Datasheet

Datasheet, Volume 2 337
Intel
®
QuickPath Architecture System Address Decode Register Description
3.2 Platform Configuration Structure
The processor contains PCI devices within a single physical component. The
configuration registers for these devices are mapped as devices residing on the PCI bus
assigned for the processor socket. Bus number is derived by the maximum bus range
setting and processor socket number.
• Device 0: Generic processor non-core
— Device 0, Function 0 contains the generic non-core configuration registers for
the processor and resides at DID (Device ID) of 2C62h.
— Device 0, Function 1 contains the System Address Decode registers and resides
at DID of 2D01h.
• Device 2: Intel QPI
— Device 2, Function 0 contains the Intel
®
QuickPath Interconnect configuration
registers for Intel QPI Link 0 and resides at DID of 2D10h.
— Device 2, Function 1 contains the physical layer registers for Intel QPI Link 0
and resides at DID of 2D11h.
Each component in the processor is uniquely identified by a PCI bus address consisting
of Bus Number, Device Number and Function Number. Device configuration is based on
the PCI Type 0 configuration conventions. All processor registers appear on the PCI bus
assigned for the processor socket. Bus number is derived by the maximum bus range
setting and processor socket number.
Table 3-2. Functions Specifically Handled by the Processor
Component Register Group DID Device Function
Processor
Intel QuickPath Architecture Generic Non-core
Registers
2C61h
0
0
Intel QuickPath Architecture System Address
Decoder
2D01h 1
Intel QPI Link 0 2D10h
2
0
Intel QPI Physical 0 2D11h 1
Intel Reserved 2D12h 2
Intel Reserved 2D13h 3