Datasheet

Processor Configuration Registers
330 Datasheet, Volume 2
2.20.4 VC0RCAP—VC0 Resource Capability Register
B/D/F/Type: 0/6/0/MMR
Address Offset: 110–113h
Reset Value: 0000_0001h
Access: RO
Bit Attr
Reset
Value
Description
31:24 RO 00h Reserved for Port Arbitration Table Offset
23 RO 0b Reserved
22:16 RO 00h Reserved for Maximum Time Slots
15 RO 0b
Reject Snoop Transactions (RSNPT)
0 = Transactions with or without the No Snoop bit set within the TLP header
are allowed on this VC.
1 = Any transaction for which the No Snoop attribute is applicable but is not
set within the TLP Header will be rejected as an Unsupported Request.
14:8 RO 0000000b
Reserved
The Port Arbitration Capability is not valid for root ports.
7:0 RO 01h
Port Arbitration Capability (PAC)
This field indicates types of Port Arbitration supported by the VC resource.
This field is valid for all Switch Ports, Root Ports that support peer-to-peer
traffic, and RCRBs, but not for PCI Express Endpoint devices or Root Ports
that do not support peer to peer traffic.
Each bit location within this field corresponds to a Port Arbitration Capability
defined below. When more than one bit in this field is Set, it indicates that
the VC resource can be configured to provide different arbitration services.
Software selects among these capabilities by writing to the Port Arbitration
Select field (see below).
Defined bit positions are:
Bit 0 =Non-configurable hardware-fixed arbitration scheme (such as, Round
Robin (RR))
Bit 1 =Weighted Round Robin (WRR) arbitration with 32 phases
Bit 2 = WRR arbitration with 64 phases
Bit 3 = WRR arbitration with 128 phases
Bit 4 = Time-based WRR with 128 phases
Bit 5 = WRR arbitration with 256 phases
Bits 6–7 = Reserved
MCH default indicates "Non-configurable hardware-fixed arbitration scheme".