Datasheet
Processor Configuration Registers
326 Datasheet, Volume 2
2.19.44 RCTL—Root Control Register
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
B/D/F/Type: 0/6/0/PCI
Address Offset: BC–BDh
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:5 RO 000h Reserved
4RO 0b
Reserved for CRS Software Visibility Enable (CSVE)
This bit, when set, enables the Root Port to return Configuration Request
Retry Status (CRS) Completion Status to software.
Root Ports that do not implement this capability must hardwire this bit to 0b.
3RW 0b
PME Interrupt Enable (PMEIE)
0 = No interrupts are generated as a result of receiving PME messages.
1 = Enables interrupt generation upon receipt of a PME message as reflected
in the PME Status bit of the Root Status Register. A PME interrupt is also
generated if the PME Status bit of the Root Status Register is set when
this bit is set from a cleared state.
2RW 0b
System Error on Fatal Error Enable (SEFEE)
This bit controls the Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = Indicates that a SERR should be generated if a fatal error is reported by
any of the devices in the hierarchy associated with this Root Port, or by
the Root Port itself.
1RW 0b
System Error on Non-Fatal Uncorrectable Error Enable (SENFUEE)
This bit controls the Root Complex's response to non-fatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = Indicates that a SERR should be generated if a non-fatal error is
reported by any of the devices in the hierarchy associated with this Root
Port, or by the Root Port itself.
0RW 0b
System Error on Correctable Error Enable (SECEE)
This bit controls the Root Complex's response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = Indicates that a SERR should be generated if a correctable error is
reported by any of the devices in the hierarchy associated with this Root
Port, or by the Root Port itself.