Datasheet

Datasheet, Volume 2 307
Processor Configuration Registers
2.19.26 PM_CS6—Power Management Control/Status Register
B/D/F/Type: 0/6/0/PCI
Address Offset: 84–87h
Reset Value: 00000008h
Access: RO, RW, RW-S
Bit Attr
Reset
Value
Description
31:16 RO 0000h
Reserved
Not Applicable or Implemented. Hardwired to 0.
15 RO 0b
PME Status (PMESTS)
Indicates that this device does not support PMEB generation from D3cold.
14:13 RO 00b
Data Scale (DSCALE)
Indicates that this device does not support the power management data
register.
12:9 RO 0h
Data Select (DSEL)
Indicates that this device does not support the power management data
register.
8RW-S 0b
PME Enable (PMEE)
Indicates that this device does not generate PMEB assertion from any D-
state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
7:4 RO 0000b Reserved
3RO 1b
No Soft Reset (NSR)
1 = When set to 1 this bit indicates that the device is transitioning from
D3hot to D0 because the power state commands do not perform a
internal reset. Config context is preserved. Upon transition no additional
operating system intervention is required to preserve configuration
context beyond writing the power state bits.
0 = When clear the devices do not perform an internal reset upon
transitioning from D3hot to D0 using software control of the power state
bits.
Regardless of this bit, the devices that transition from a D3hot to D0 by a
system or bus segment reset will return to the device state D0 uniintialized
with only PME context preserved if PME is supported and enabled.
2RO 0bReserved
1:0 RW 00b
Power State (PS)
This field indicates the current power state of this device and can be used to
set the device into a new power state. If software attempts to write an
unsupported state to this field, write operation must complete normally on
the bus, but the data is discarded and no state change occurs.
00 =D0
01 =D1 (Not supported in this device.)
10 = D2 (Not supported in this device.)
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This device also
cannot generate interrupts or respond to MMR cycles in the D3 state. The
device must return to the D0 state in order to be fully-functional.
When the Power State is other than D0, the bridge will Master Abort (that is,
not claim) any downstream cycles (with exception of type 0 config cycles).
Consequently, these unclaimed cycles will go down DMI and come back up as
Unsupported Requests, which the MCH logs as Master Aborts in Device 0
PCISTS[13]
There is no additional hardware functionality required to support these Power
States.