Datasheet

Processor Configuration Registers
306 Datasheet, Volume 2
2.19.25 PM_CAPID6—Power Management Capabilities Register
B/D/F/Type: 0/6/0/PCI
Address Offset: 80–83h
Reset Value: C8039001h
Access: RO
Bit Attr
Reset
Value
Description
31:27 RO 19h
PME Support (PMES)
This field indicates the power states in which this device may indicate PME
wake using PCI Express messaging. D0, D3hot & D3cold. This device is not
required to do anything to support D3hot & D3cold, it simply must report that
those states are supported. Refer to the PCI Power Management 1.1
specification for encoding explanation and other power management details.
26 RO 0b
D2 Power State Support (D2PSS)
Hardwired to 0 to indicate that the D2 power management state is NOT
supported.
25 RO 0b
D1 Power State Support (D1PSS)
Hardwired to 0 to indicate that the D1 power management state is NOT
supported.
24:22 RO 000b
Auxiliary Current (AUXC)
Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary current
requirements.
21 RO 0b
Device Specific Initialization (DSI)
Hardwired to 0 to indicate that special initialization of this device is NOT
required before generic class device driver is to use it.
20 RO 0b
Auxiliary Power Source (APS)
Hardwired to 0.
19 RO 0b
PME Clock (PMECLK)
Hardwired to 0 to indicate this device does NOT support PMEB generation.
18:16 RO 011b
PCI PM CAP Version (PCIPMCV)
Version - A value of 011b indicates that this function complies with revision
1.2 of the PCI Power Management Interface Specification.
15:8 RO 90h
Pointer to Next Capability (PNC)
This field contains a pointer to the next item in the capabilities list. If MSICH
(CAPL[0] @ 7Fh) is 0, then the next item in the capabilities list is the
Message Signaled Interrupts (MSI) capability at 90h. If MSICH (CAPL[0] @
7Fh) is 1, then the next item in the capabilities list is the PCI Express
capability at A0h.
7:0 RO 01h
Capability ID (CID)
Value of 01h identifies this linked list item (capability structure) as being for
PCI Power Management registers.