Datasheet

Datasheet, Volume 2 305
Processor Configuration Registers
9RO 0b
Secondary Discard Timer (SDT)
Not Applicable or Implemented. Hardwired to 0.
8RO 0b
Primary Discard Timer (PDT)
Not Applicable or Implemented. Hardwired to 0.
7RO 0b
Fast Back-to-Back Enable (FB2BEN)
Not Applicable or Implemented. Hardwired to 0.
6RW 0b
Secondary Bus Reset (SRESET)
Setting this bit triggers a hot reset on the corresponding PCI Express Port.
This will force the LTSSM to transition to the Hot Reset state (using Recovery)
from L0, L0s, or L1 states.
5RO 0b
Master Abort Mode (MAMODE)
Does not apply to PCI Express. Hardwired to 0.
4RW 0b
VGA 16-bit Decode (VGA16D)
Enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address
precluding the decoding of alias addresses every 1 KB. This bit only has
meaning if bit 3 (VGA Enable) of this register is also set to 1, enabling VGA
I/O decoding and forwarding by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
3RW 0b
VGA Enable (VGAEN)
This bit controls the routing of processor initiated transactions targeting VGA
compatible I/O and memory address ranges. See the VGAEN/MDAP table in
device 0, offset 97h[0].
2RW 0b
ISA Enable (ISAEN)
Needed to exclude legacy resource decode to route ISA resources to legacy
decode path. Modifies the response by the GMCH to an I/O access issued by
the processor that target ISA I/O addresses. This applies only to I/O
addresses that are enabled by the IOBASE and IOLIMIT registers.
0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions will be mapped to PCI Express-G.
1 = GMCH will not forward to PCI Express-G any I/O transactions addressing
the last 768 bytes in each 1 KB block even if the addresses are within
the range defined by the IOBASE and IOLIMIT registers.
1RW 0b
SERR Enable (SERREN)
0 = No forwarding of error messages from secondary side to primary side
that could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR
message when individually enabled by the Root Control register.
0RW 0b
Parity Error Response Enable (PEREN)
This bit controls whether or not the Master Data Parity Error bit in the
Secondary Status register is set when the MCH receives across the link
(upstream) a Read Data Completion Poisoned TLP.
0 = Master Data Parity Error bit in Secondary Status register can NOT be
set..
1 = Master Data Parity Error bit in Secondary Status register CAN be set.
B/D/F/Type: 0/6/0/PCI
Address Offset: 3E–3Fh
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description