Datasheet

Processor Configuration Registers
304 Datasheet, Volume 2
2.19.22 INTRLINE6—Interrupt Line Register
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
2.19.23 INTRPIN6—Interrupt Pin Register
This register specifies which interrupt pin this device uses.
2.19.24 BCTRL6—Bridge Control Register
This register provides extensions to the PCICMD6 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (that is, PCI
Express-G) as well as some bits that affect the overall behavior of the "virtual" Host-
PCI Express bridge embedded within GMCH (such as, VGA compatible address ranges
mapping).
B/D/F/Type: 0/6/0/PCI
Address Offset: 3Ch
Reset Value: 00h
Access: RW
Bit Attr
Reset
Value
Description
7:0 RW 00h
Interrupt Connection (INTCON)
This field is used to communicate interrupt line routing information.
BIOS Requirement: POST software writes the routing information into this
register as it initializes and configures the system. The value indicates to
which input of the system interrupt controller this device's interrupt pin is
connected.
B/D/F/Type: 0/6/0/PCI
Address Offset: 3Dh
Reset Value: 01h
Access: RO
Bit Attr
Reset
Value
Description
7:0 RO 01h
Interrupt Pin (INTPIN)
As a single function device, the PCI Express device specifies INTA as its
interrupt pin. 01h=INTA.
B/D/F/Type: 0/6/0/PCI
Address Offset: 3E–3Fh
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:12 RO 0h Reserved
11 RO 0b
Discard Timer SERR# Enable (DTSERRE)
Not Applicable or Implemented. Hardwired to 0.
10 RO 0b
Discard Timer Status (DTSTS)
Not Applicable or Implemented. Hardwired to 0.