Datasheet
Datasheet, Volume 2 303
Processor Configuration Registers
2.19.20 PMLIMITU6—Prefetchable Memory Limit Address Upper
Register
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1 MB aligned memory block.
Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that must be defined as UC and the
ones that can be designated as a USWC (that is, prefetchable) from the processor
perspective.
2.19.21 CAPPTR6—Capabilities Pointer Register
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
B/D/F/Type: 0/6/0/PCI
Address Offset: 2C–2Fh
Reset Value: 00000000h
Access: RW
Bit Attr
Reset
Value
Description
31:0 RW 00000000
h
Prefetchable Memory Address Limit (MLIMITU)
This field corresponds to A[63:32] of the upper limit of the prefetchable
Memory range that will be passed to PCI Express-G.
B/D/F/Type: 0/6/0/PCI
Address Offset: 34h
Reset Value: 88h
Access: RO
Bit Attr
Reset
Value
Description
7:0 RO 88h
First Capability (CAPPTR1)
The first capability in the list is the Subsystem ID and Subsystem Vendor ID
Capability.