Datasheet

Processor Configuration Registers

302 Datasheet, Volume 2

2.19.19 PMBASEU6—Prefetchable Memory Base Address Upper

The functionality associated with this register is present in the PEG design

implementation.

This register in conjunction with the corresponding Upper Base Address register

controls the processor to PCI Express-G prefetchable memory access routing based on

the following formula:

PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of this register are read/write and correspond to address bits

A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are

read/write and correspond to address bits A[39:32] of the 40-bit address. This register

must be initialized by the configuration software. For the purpose of address decode,

address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory

address range will be aligned to a 1 MB boundary.

B/D/F/Type: 0/6/0/PCI

Address Offset: 28–2Bh

Reset Value: 0000_0000h

Access: RW

Bit Attr

Reset

Value

Description

31:0 RW

0000_000

Prefetchable Memory Base Address (MBASEU)

This field corresponds to A[63:32] of the lower limit of the prefetchable

memory range that will be passed to PCI Express-G.