Datasheet
Processor Configuration Registers
290 Datasheet, Volume 2
2.19.2 DID6—Device Identification Register
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
2.19.3 PCICMD6—PCI Command Register
B/D/F/Type: 0/6/0/PCI
Address Offset: 2–3h
Reset Value: 0043h
Access: RO
Bit Attr
Reset
Value
Description
15:4 RO 004h
Device Identification Number Upper Bits (DID6UB)
Identifier assigned to device 6 (virtual PCI-to-PCI bridge, PCI Express
Graphics port).
3:2 RO 00b
Device Identification Number Hardware controlled (DID6HW)
Identifier assigned to the device 6 (virtual PCI-to-PCI bridge, PCI Express
Graphics port).
1:0 RO 11b
Device Identification Number Lower Bits (DID6LB)
Identifier assigned to the device 6 (virtual PCI-to-PCI bridge, PCI Express
Graphics port).
B/D/F/Type: 0/6/0/PCI
Address Offset: 4–5h
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:11 RO 00h Reserved
10 RW 0b
INTA Assertion Disable (INTAAD)
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages. Any INTA
emulation interrupts already asserted must be de-asserted when this bit
is set.
Only affects interrupts generated by the device (PCI INTA from a PME or Hot
Plug event) controlled by this command register. It does not affect upstream
MSIs, upstream PCI INTA-INTD assert and de-assert messages.
9RO 0b
Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. Hardwired to 0.
8RW 0b
SERR# Message Enable (SERRE6)
This bit controls Device 6 SERR# messaging. The root port communicates the
SERR# condition by sending an SERR message to the PCH. This bit, when
set, enables reporting of non-fatal and fatal errors detected by the device to
the Root Complex. Note that errors are reported if enabled either through
this bit or through the PCI-Express specific bits in the Device Control
Register.
In addition, for Type 1 configuration space header devices, this bit, when set,
enables transmission by the primary interface of ERR_NONFATAL and
ERR_FATAL error messages forwarded from the secondary interface. This bit
does not affect the transmission of forwarded ERR_COR messages.
0 = The SERR message is generated by the root port only under conditions
enabled individually through the Device Control Register.
1 = The root port is enabled to generate SERR messages which will be sent
to the PCH for specific root port error conditions generated/detected or
received on the secondary side of the virtual PCI to PCI bridge. The
status of SERRs generated is reported in the PCISTS6 register.