Datasheet

Datasheet, Volume 2 285
Processor Configuration Registers
56:50 RO 00h Reserved
49 RW 0b
Drain Reads (DR)
This field is ignored by hardware if the DRD field is reported as clear in the
Capability register.
When DRD field is reported as set in the Capability register, the following
encodings are supported for this field:
0 = Hardware may complete the IOTLB invalidation without draining DMA
read requests.
1 = Hardware must drain DMA read requests.
Refer VTd specification for description of DMA draining.
48 RW 0b
Drain Writes (DW)
This field is ignored by hardware if the DWD field is reported as clear in the
Capability register.
When DWD field is reported as set in the Capability register, the following
encodings are supported for this field:
0 = Hardware may complete the IOTLB invalidation without draining DMA
write requests.
1 = Hardware must drain relevant translated DMA write requests.
Refer VTd specification for description of DMA draining.
47:32 RW 0000h
Domain-ID (DID)
Indicates the ID of the domain whose IOTLB entries need to be selectively
invalidated. This field must be programmed by software for domain-selective
and page-selective invalidation requests.
The Capability register reports the domain-id width supported by hardware.
Software must ensure that the value written to this field is within this limit.
Hardware ignores and not implement bits 47:(32+N), where N is the
supported domain-id width reported in the Capability register.
31:0 RO
0000_000
0h
Reserved
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: 108–10Fh
Reset Value: 0200000000000000h
Access: RW, RO
Bit Attr
Reset
Value
Description