Datasheet
Datasheet, Volume 2 283
Processor Configuration Registers
2.18.27 IVA_REG—Invalidate Address Register
This register provides the DMA address whose corresponding IOTLB entry needs to be
invalidated through the corresponding IOTLB Invalidate register. The register is a write-
only register. A value returned on a read of this register is undefined.
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: 100–107h
Reset Value: 0000000000000000h
Access: RO
Bit Attr
Reset
Value
Description
63:36 RO 0000000h Reserved
35:12 RO 000000h
Address (ADDR)
Software provides the DMA address that needs to be page-selectively
invalidated. To make a page-selective invalidation request to hardware,
software must first write the appropriate fields in this register, and then issue
appropriate page-selective invalidate command through the IOTLB_REG.
Hardware ignores bits 63:N, where N is the maximum guest address width
(MGAW) supported.
Value returned on read of this field is undefined.
11:7 RO 00h Reserved
6RO 0b
Invalidation Hint (IH)
The field provides hints to hardware about preserving or flushing the non-leaf
(page directory) entries that may be cached in hardware:
0 = Software may have modified both leaf and non-leaf page-table entries
corresponding to mappings specified in the ADDR and AM fields. On a
page-selective invalidation request, hardware must flush both the
cached leaf and non-leaf page-table entries corresponding to the
mappings specified by ADDR and AM fields.
1 = Software has not modified any non-leaf page-table entries
corresponding to mappings specified in the ADDR and AM fields. On a
page-selective invalidation request, hardware may preserve the cached
non-leaf page-table entries corresponding to the mappings specified by
the ADDR and AM fields.
A value returned on a read of this field is undefined.
5:0 RO 00h
Address Mask (AM)
The value in this field specifies the number of low order bits of the ADDR field
that must be masked for the invalidation operation. Mask field enables
software to request invalidation of contiguous mappings for size-aligned
regions. For example:
Mask Value ADDR bits masked Pages invalidated
0 None 1
112 2
2 13:12 4
3 14:12 8
4 15:12 16
5 16:12 32
6 17:12 64
7 18:12 128
8 19:12 256
Hardware implementations report the maximum supported mask value
through the Capability register.
Value returned on read of this field is undefined.