Datasheet
Processor Configuration Registers
282 Datasheet, Volume 2
2.18.26 IRTA_REG—Interrupt Remapping Table Address Register
This register provides the base address of Interrupt remapping table. The register is
treated as reserved by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: B8–BFh
Reset Value: 0000000000000000h
Access: RO
Bit Attr
Reset
Value
Description
63:12 RO 00..00b
Interrupt Remapping Table Address (IRTA)
This field points to the base of 4 KB aligned interrupt remapping table.
Hardware ignores and not implement bits 63:HAW, where HAW is the host
address width.
Reads of this field returns value that was last programmed to it.
11 RO 0b
Extended Interrupt Mode Enable (EIME)
0 = Legacy interrupt mode is active. Hardware interprets only low 8 bits of
Destination-ID field in the IRTEs. The high 24 bits of the Destination-ID
field is treated as reserved. On the processor platforms hardware
interprets the low 16 bits of the Destination-ID field in the IRTEs and
treats the high 16 bits as reserved.
1 = Intel 64 platform is operating in Extended Interrupt Mode. Hardware
interprets all 32 bits of the Destination-ID field in the IRTEs.
Hardware reporting Extended Interrupt Mode (EIM) as Clear in the Capability
register treats this field as reserved.
10:4 RO 00h Reserved
3:0 RO 0h
Size (S)
This field specifies the size of the interrupt remapping table. The number of
entries in the interrupt remapping table is 2^^(X+1), where X is the value
programmed in this field.