Datasheet

Datasheet, Volume 2 279
Processor Configuration Registers
2.18.21 IQA_REG—Invalidation Queue Address Register
This register is used to configure the base address and size of the invalidation queue.
The register is treated as reserved by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
When supported, writing to this register causes the Invalidation Queue Head and
Invalidation Queue Tail registers to be reset to 0h.
2.18.22 ICS_REG—Invalidation Completion Status Register
This register reports completion status of invalidation wait descriptor with Interrupt
Flag (IF) Set. The register is treated as reserved by implementations reporting Queued
Invalidation (QI) as not supported in the Extended Capability register.
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: 90–97h
Reset Value: 0000000000000000h
Access: RO
Bit Attr
Reset
Value
Description
63:12 RO 00..00b
Invalidation Queue Address (IQA)
This field points to the base of 4 KB aligned invalidation request queue.
Hardware ignores and not implement bits 63:HAW, where HAW is the host
address width.
Reads of this field return the value that was last programmed to it.
11:3 RO 000h Reserved
2:0 RO 000b
Queue Size (QS)
This field specifies the size of the invalidation request queue. A value of X in
this field indicates an invalidation request queue of (X+1) 4 KB pages. The
number of entries in the invalidation queue is 2^^(X + 8).
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: 9C–9Fh
Reset Value: 00000000h
Access: RO
Bit Attr
Reset
Value
Description
31:1 RO 00..00b Reserved
0RO 0b
Invalidation Wait Descriptor Complete (IWC)
This bit indicates completion of Invalidation Wait Descriptor with Interrupt
Flag (IF) field Set.
Hardware implementations not supporting queued invalidations implement
this field as reserved.