Datasheet

Datasheet, Volume 2 277
Processor Configuration Registers
2.18.18 PHMLIMIT_REG—Protected High Memory Limit Register
This register is used to set up the limit address of DMA-protected high-memory region.
The register must be set up before enabling protected memory through PMEN_REG,
and must not be updated when protected memory regions are enabled.
When the LT CMD.LOCK.PMRC command is invoked, this register is locked (treated as
RO). When the LT CMD.UNLOCK.PMRC command is invoked, this register is unlocked
(treated as RW).
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as 0 in the Capability register).
The alignment of the protected high memory region limit depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1’s to this
register, and finding most significant zero bit position below host address width (HAW)
in the value read back from the register. Bits N:0 of the limit register are decoded by
hardware as all 1s.
The protected high-memory base & limit registers function as follows.
• in bits HAW:(N+1) specifies a protected low-memory region of size 2^^(N+1)
bytes.
• Programming the protected high-memory limit register with a value less than the
protected high-memory base register disables the protected high-memory region.
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: 78–7Fh
Reset Value: 0000000000000000h
Access: RO, RW
Bit Attr
Reset
Value
Description
63:36 RO 0000000h Reserved
35:21 RW 0000h
Protected High-Memory Limit (PHML)
This field specifies the last host physical address of the DMA-protected high-
memory region in system memory.
Hardware ignores and does not implement bits 63:HAW, where HAW is the
host address width.
20:0 RO 000000h Reserved