Datasheet

Datasheet, Volume 2 271
Processor Configuration Registers
2.18.10 FEDATA_REG—Fault Event Data Register
This register specifies the interrupt message data.
2.18.11 FEADDR_REG—Fault Event Address Register
This register specifies the interrupt message address.
2.18.12 FEUADDR_REG—Fault Event Upper Address Register
This register specifies the interrupt message upper address. This register is treated as
reserved by implementations reporting Extended Interrupt Mode (EIM) as not
supported in the Extended Capability register.
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: 3C–3Fh
Reset Value: 00000000h
Access: RO, RW
Bit Attr
Reset
Value
Description
31:16 RO 0000h
Extended Interrupt Message Data (EID)
This field is valid only for implementations supporting 32-bit interrupt data
fields.
Hardware implementations supporting only 16-bit interrupt data treat this
field as reserved.
15:0 RW 0000h
Interrupt message data (ID)
Data value in the interrupt request. Software requirements for programming
this register are described in the VTd specification.
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: 40–43h
Reset Value: 0000_0000h
Access: RW, RO
Bit Attr
Reset
Value
Description
31:2 RW
0000_000
0h
Message Address (MA)
When fault events are enabled, the contents of this register specify the
DWORD-aligned address (bits 31:2) for the interrupt request.
Software requirements for programming this register are described in the
VTd specification.
1:0 RO 00b Reserved
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: 44–47h
Reset Value: 0000_0000h
Access: RO
Bit Attr
Reset
Value
Description
31:0 RO
0000_000
0h
Message Upper Address (MUA)
Hardware implementations supporting Extended Interrupt Mode are required
to implement this register.
Software requirements for programming this register are described in the
VTd specification.
Hardware implementations not supporting Extended Interrupt Mode may
treat this field as reserved.