Datasheet
Processor Configuration Registers
260 Datasheet, Volume 2
2.18.3 ECAP_REG—Extended Capability Register
This register reports DMA-remapping hardware extended capabilities.
B/D/F/Type: 0/2/0/GFXVTBAR
Address Offset: 10–17h
Reset Value: 0000000000001000h
Access: RO
Bit Attr
Reset
Value
Description
63:24 RO 0h Reserved
23:20 RO 0h
Maximum Handle Mask Value (MHMV)
The value in this field indicates the maximum supported value for the Handle
Mask (HM) field in the interrupt entry cache invalidation descriptor
(iec_inv_dsc).
This field is valid only when the IR field is reported as Set.
19:18 RO 00b Reserved
17:8 RO 010h
Invalidation Unit Offset (IVO)
This field specifies the offset to the IOTLB invalidation register relative to the
register base address of this remapping hardware unit.
If the register base address is X, and the value reported in this field is Y, the
address for the IOTLB invalidation register is calculated as X+(16*Y).
7RO 0b
Snoop Control (SC)
0 = Hardware does not support setting the SNP field to 1 in the page-table
entries.
1 = Hardware supports setting the SNP field to 1 in the page-table entries.
6RO 0b
Pass Through (PT)
0 = Hardware does not support pass through translation type in context
entries.
1 = Hardware supports pass-through translation type in context entries.
5RO 0b
Caching Hints (CH)
0 = Hardware does not support IOTLB caching hints (ALH and EH fields in
context-entries are treated as reserved).
1 = Hardware supports IOLTB caching hints through the ALH and EH fields in
context-entries.
4RO 0b
Extended Interrupt Mode (EIM)
0 = Hardware supports only 8-bit APICIDs (Legacy Interrupt Mode) on Intel
64 and IA-32 platforms and 16-bit APIC-IDs on the processor platforms.
1 = Hardware supports Extended Interrupt Mode (32-bit APIC-IDs) on Intel
64 platforms.
This field is valid only when the IR field is reported as Set.
3RO 0b
Interrupt Remapping (IR)
0 = Hardware does not support interrupt remapping.
1 = Hardware supports interrupt remapping.
Implementations reporting this field as Set must also support Queued
Invalidation (QI = 1b).
2RO 0b
Device IOTLB Support (DI)
0 = Hardware does not support device-IOTLBs.
1 = Hardware supports Device-IOTLBs.
Implementations reporting this field as Set must also support Queued
Invalidation (QI = 1b).
1RO 0b
Queued Invalidation (QI)
0 = Hardware does not support queued invalidations.
1 = Hardware supports queued invalidations.