Datasheet
Datasheet, Volume 2 247
Processor Configuration Registers
2.16.26 IEUADDR_REG—Invalidation Event Upper Address
Register
This register specifies the Invalidation Event interrupt message upper address. This
register is treated as reserved by implementations reporting both Queued Invalidation
(QI) and Extended Interrupt Mode (EIM) as not supported in the Extended Capability
register.
2.16.27 IRTA_REG—Interrupt Remapping Table Address Register
This register provides the base address of Interrupt remapping table. The register is
treated as reserved by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: AC–AFh
Reset Value: 0000_0000h
Access: RO
Bit Attr
Reset
Value
Description
31:0 RO
0000_000
0h
Message Upper Address (MUA)
Hardware implementations supporting Queued Invalidations and Extended
Interrupt Mode are required to implement this register.
Software requirements for programming this register are described in the
VTd specification. Hardware implementations not supporting Queued
Invalidations and Extended Interrupt Mode may treat this field as reserved.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: B8–BFh
Reset Value: 0000000000000000h
Access: RO
Bit Attr
Reset
Value
Description
63:12 RO
00000000
00000h
Interrupt Remapping Table Address (IRTA)
This field points to the base of the 4 KB aligned interrupt remapping table.
Hardware ignores and not 63:HAW, where HAW is the width.
Reads of this field returns last value programmed to it.
11 RO 0b
Extended Interrupt Mode Enable (EIMI)
0 = xAPIC mode is active. Hardware interprets only low 8-bits of
Destination-ID field in the IRTEs. The high 24 bits of the Destination-ID
field are treated as reserved. On the processor platforms hardware
interprets low 16-bits of Destination-ID field in the IRTEs and treats the
high 16-bits as reserved.
1 = x2APIC mode is active. Hardware interprets all 32-bits of the
Destination-ID field in the IRTEs.
Hardware reporting Extended Interrupt Mode (EIM) as Clear in the Capability
register treats this field as reserved.
10:4 RO 00h Reserved
3:0 RO 0h
Size (S)
This field specifies the size of the interrupt remapping table. The number of
entries in the interrupt remapping table is 2^(X+1), where X is the value
programmed in this field.