Datasheet

Processor Configuration Registers
246 Datasheet, Volume 2
2.16.24 IEDATA_REG—Invalidation Event Data Register
This register specifies the Invalidation Event interrupt message data. This register is
treated as reserved by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
2.16.25 IEADDR_REG—Invalidation Event Address Register
This register specifies the Invalidation Event Interrupt message address. This register
is treated as reserved by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: A4–A7h
Reset Value: 00000000h
Access: RO
Bit Attr
Reset
Value
Description
31:16 RO 0000h
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit interrupt data
fields.
Hardware implementations supporting only 16-bit interrupt data treat this
field as reserved.
15:0 RO 0000h
Interrupt Message Data (IMD)
Data value in the interrupt request. Software requirements for programming
this register are described in the VTd specification.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: A8–ABh
Reset Value: 00000000h
Access: RO
Bit Attr
Reset
Value
Description
31:2 RO
00000000
h
Message Address (MA)
When fault events are enabled, the contents of this register specify the
DWORD-aligned address (bits 31:2) for the interrupt request.
Software requirements for programming this register are described in the
VTd specification Section 5.7.
1:0 RO 00b Reserved