Datasheet

Datasheet, Volume 2 243
Processor Configuration Registers
2.16.19 IQH_REG—Invalidation Queue Head Register
This register indicates the invalidation queue head. This register is treated as reserved
by implementations reporting Queued Invalidation (QI) as not supported in the
Extended Capability register.
2.16.20 IQT_REG—Invalidation Queue Tail Register
This register indicates the invalidation tail head. This register is treated as reserved by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: 80–87h
Reset Value: 0000000000000000h
Access: RO
Bit Attr
Reset
Value
Description
63:19 RO
00000000
0000h
Reserved
18:4 RO 0000h
Queue Head (QH)
Specifies the offset (128-bit aligned) to the invalidation queue for the
command that will be fetched next by hardware. Hardware resets this field to
0 whenever the queued invalidation is disabled (QIES field Clear in the Global
Status register).
3:0 RO 0h Reserved
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: 88–8Fh
Reset Value: 0000000000000000h
Access: RO
Bit Attr
Reset
Value
Description
63:19 RO
00000000
0000h
Reserved
18:4 RO 0000h
Queue Tail (QT)
Specifies the offset (128-bit aligned) to the invalidation queue for the
command that will be written next by software.
3:0 RO 0h Reserved