Datasheet
Processor Configuration Registers
238 Datasheet, Volume 2
2.16.14 PMEN_REG—Protected Memory Enable Register
This register enables the DMA-protected memory regions set up through the PLMBASE,
PLMLIMT, PHMBASE, PHMLIMIT registers. This register is treated as RO for
implementations not supporting protected memory regions (PLMR and PHMR fields
reported as Clear in the Capability register).
Protected memory regions may be used by software to securely initialize remapping
structures in memory.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: 64–67h
Reset Value: 00000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
31 RW 0b
Enable Protected Memory (EPM)
This field controls DMA accesses to the protected low-memory and protected
high memory regions.
0 = Protected memory regions are disabled.
1 = Protected memory regions are enabled.
DMA requests accessing protected memory regions are handled as follows:
When DMA remapping is not enabled, all DMA requests accessing protected
memory regions are blocked.
When DMA remapping is enabled:
DMA requests processed as pass-through (Translation Type value of 10b in
Context-Entry) and accessing the protected memory regions are blocked.
DMA requests with translated address (AT=10b) and accessing the protected
memory regions are blocked.
DMA requests that are subject to address remapping, and accessing the
protected memory regions may or may not be blocked by hardware. For such
requests, software must not depend on hardware protection of the protected
memory regions, and instead program the DMA-remapping page-tables to
not allow DMA to protected memory regions.
Remapping hardware access to the remapping structures are not subject to
protected memory region checks.
DMA requests blocked due to protected memory region violation are not
recorded or reported as remapping faults.
Hardware reports the status of the protected memory enable/disable
operation through the PRS field in this register. Hardware implementations
supporting DMA draining must drain any in-flight translated DMA requests
queued within the Root-Complex before indicating the protected memory
region as enabled through the PRS field.
30:1 RO 00..00b Reserved
0RO 0b
Protected Region Status (PRS)
This field indicates the status of protected memory region.
0 = Protected memory region(s) not enabled.
1 = Protected memory region(s) enabled.