Datasheet

Processor Configuration Registers
236 Datasheet, Volume 2
2.16.10 FEDATA_REG—Fault Event Data Register
This register specifies the interrupt message data.
2.16.11 FEADDR_REG—Fault Event Address Register
This Register specifies the interrupt message address.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: 3C–3Fh
Reset Value: 00000000h
Access: RO, RW
Bit Attr
Reset
Value
Description
31:16 RO 0000h
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit MSI data fields.
Hardware implementations supporting only 16-bit MSI data may treat this
field as read-only (0).
15:0 RW 0000h
Interrupt message Data (ID)
Data value in the interrupt request. Software requirements for programming
this register are described in the VTd specification.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: 40–43h
Reset Value: 00000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
31:2 RW
00000000
h
Message Address (MA)
When fault events are enabled, the contents of this register specify the
DWORD aligned address (bits 31:2) for the interrupt request.
Software requirements for programming this register are described in the
VTd specification.
1:0 RO 00b Reserved