Datasheet

Datasheet, Volume 2 235
Processor Configuration Registers
2.16.9 FECTL_REG—Fault Event Control Register
This register specifies the fault event interrupt message control bits. The VTd
specification describes hardware handling of fault events.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: 38-3Bh
Reset Value: 80000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
31 RW 1b
Interrupt Mask (IM)
0 = No masking of interrupt. When a interrupt condition is detected,
hardware issues an interrupt message (using the Fault Event Data &
Fault Event Address register values).
1 = This is the value on reset. Software may mask interrupt message
generation by setting this field. Hardware is prohibited from sending the
interrupt message when this field is set.
30 RO 0b
Interrupt Pending (IP)
Hardware sets the IP field whenever it detects an interrupt condition, which is
defined as:
• When primary fault logging is active, an interrupt condition occurs when
hardware records a fault through one of the Fault Recording registers
and sets the PPF field in the Fault Status register.
• When advanced fault logging is active, an interrupt condition occurs
when hardware records a fault in the first fault record (at index 0) of the
current fault log and sets the APF field in the Fault Status register.
• Hardware detected error associated with the Invalidation Queue, setting
the IQE field in the Fault Status register.
• Hardware detected invalid Device-IOTLB invalidation completion, setting
the ICE field in the Fault Status register.
• Hardware detected Device-IOTLB invalidation completion time-out,
setting the ITE field in the Fault Status register.
If any of the status fields in the Fault Status register was already Set at the
time of setting any of these fields, it is not treated as a new interrupt
condition.
The IP field is kept Set by hardware while the interrupt message is held
pending. The interrupt message could be held pending due to the interrupt
mask (IM field) being Set or other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced.
This could be due to either:
• Hardware issuing the interrupt message due to either a change in the
transient hardware condition that caused the interrupt message to be
held pending, or due to software clearing the IM field.
• Software servicing all the pending interrupt status fields in the Fault
Status register as follows.
— When primary fault logging is active, software clearing the Fault
(F) field in all the Fault Recording registers with faults, causing the
PPF field in the Fault Status register to be evaluated as Clear.
— Software clearing other status fields in the Fault Status register by
writing back the value read from the respective fields.
29:0 RO 00..00h Reserved