Datasheet
Datasheet, Volume 2 229
Processor Configuration Registers
24 RO 0b
Set Interrupt Remap Table Pointer (SIRTP)
This field is valid only for implementations supporting interrupt-remapping.
Software sets this field to set/update the interrupt remapping table pointer
used by hardware. The interrupt remapping table pointer is specified through
the Interrupt Remapping Table Address register.
Hardware reports the status of the interrupt remapping table pointer set
operation through the IRTPS field in the Global Status register. The interrupt
remap table pointer set operation must be performed before enabling or re-
enabling (after disabling) interrupt-remapping hardware through the IRE
field.
After an interrupt remap table pointer set operation, software must globally
invalidate the interrupt entry cache. This is required to ensure hardware uses
only the interrupt-remapping entries referenced by the new interrupt remap
table pointer, and not any stale cached entries.
While interrupt remapping is active, software may update the interrupt
remapping table pointer through this field. However, to ensure valid in-flight
interrupt requests are deterministically remapped, software must ensure that
the structures referenced by the new interrupt remap table pointer are
programmed to provide the same remapping results as the structures
referenced by the previous interrupt remap table pointer.
Clearing this bit has no effect. The value returned on a read of this field is
undefined.
23 RO 0b
Compatibility Format Interrupt (CFI)
This field is valid only for Intel 64 implementations supporting interrupt-
remapping. Software writes to this field to enable or disable Compatibility
Format interrupts on Intel 64 platforms. The value in this field is effective
only when interrupt-remapping is enabled and Extended Interrupt Mode
(x2APIC mode) is disabled.
0 = Block Compatibility format interrupts.
1 = Process Compatibility format interrupts as pass-through (bypass
interrupt remapping).
Hardware reports the status of updating this field through the CFIS field in
the Global Status register.
Refer to the VTd specification for details on Compatibility Format interrupt
requests.
The value returned on a read of this field is undefined.
This field is not implemented.
22:0 RO 000000h Reserved
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: 18–1Bh
Reset Value: 00000000h
Access: W, RO
Bit Attr
Reset
Value
Description