Datasheet

Processor Configuration Registers
226 Datasheet, Volume 2
17:8 RO 010h
Invalidation Unit Offset (IVO)
This field specifies the location to the first IOTLB registers relative to the
register base address of this DMA-remapping hardware unit.
If the register base address is X, and the value reported in this field is Y, the
address for the first IOTLB register is calculated as X+(16*Y).
7RO 0b
Snoop Control (SC)
0 = Hardware does not support setting the SNP field to '1' in the page-table
entries.
1 = Hardware supports setting the SNP field to '1' in the page-table entries.
6RO 0b
Pass Through (PT)
0 = Hardware does not support pass-through translation type in context
entries.
1 = Hardware supports pass-through translation type in context entries.
5RO 0b
Caching Hints (CH)
0 = Hardware does not support IOTLB caching hints (ALH and EH fields in
context-entries are treated as reserved).
1 = Hardware supports IOLTB caching hints through the ALH and EH fields in
context-entries.
4RO 0b
Extended Interrupt Mode (EIM)
0 = On Intel 64 platforms, hardware supports only 8-bit APIC-IDs (xAPIC
Mode).
1 = On Intel 64 platforms, hardware supports 32-bit APIC-IDs (x2APIC
mode).
The processor supports 16-bit APICIDs and always report this field as 0.
This field is valid only when the IR field is reported as Set.
3RO 0b
Interrupt Remapping Support (IR)
0 = Hardware does not support interrupt remapping.
1 = Hardware supports interrupt remapping.
Implementations reporting this field as Set must also support Queued
Invalidation (QI = 1b).
2RO 0b
Device IOTLB Support (DI)
0 = Hardware does not support device-IOTLBs.
1 = Hardware supports Device-IOTLBs.
Implementations reporting this field as Set must also support Queued
Invalidation (QI = 1b).
1RO 0b
Queued Invalidation Support (QI)
0 = Hardware does not support queued invalidations.
1 = Hardware supports queued invalidations.
0RO 0b
Coherency (C)
This field indicates if hardware access to the root, context, page-table and
interrupt remap structures are coherent (snooped) or not.
0 = Indicates hardware accesses to remapping structures are noncoherent.
1 = Indicates hardware accesses to remapping structures are coherent.
Hardware access to advanced fault log and invalidation queue are always
coherent.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: 10–17h
Reset Value: 0000000000001000h
Access: RO
Bit Attr
Reset
Value
Description