Datasheet

Processor Configuration Registers
22 Datasheet, Volume 2
2.2.2.2 TSEG
The TSEG register was moved from the GMCH to the processor. The GMCH will have no
direct knowledge of the TSEG size. For processor initiated transactions, the processor
will perform necessary decode and route appropriately on HOM (to DRAM) or NCS/NCB.
TSEG is below IGD stolen memory, which is at the Top of Low Usable physical memory
(TOLUD). When SMM is enabled, the maximum amount of memory available to the
system is equal to the amount of physical DRAM minus the value in the TSEG register.
BIOS will calculate and program a register, so the GMCH has knowledge of where
(TOLUD) – (Gfx stolen) – (Gfx GTT stolen) – (TSEG) is located. This is indicated by the
TSEG_BASE register.
SMM-mode processor accesses to enabled TSEG access the physical DRAM at the same
address. The processor will route these accesses on the QPI HOM channel.
When the extended SMRAM space is enabled, processor accesses to the TSEG range
without SMM attribute or without WB attribute are handled by the processor as invalid
accesses. Refer to the processor documentation for how the processor handles these
accesses.
Non- processor originated accesses are not allowed to SMM space. PCI-Express, DMI,
and Internal Graphics originated cycle to enabled SMM space are handled as invalid
cycle type with reads and writes to location 0 and byte enables turned off for writes.
2.2.2.3 Protected Memory Range (PMR) – (programmable)
For robust and secure launch of the MVMM, the MVMM code and private data needs to
be loaded to a memory region protected from bus master accesses. Support for
protected memory region is required for DMA-remapping hardware implementations on
platforms supporting Intel
®
Trusted Execution Technology (Intel TXT), and is optional
for non-Intel TxT platforms. Since the protected memory region needs to be enabled
before the MVMM is launched, hardware must support enabling of the protected
memory region independently from enabling the DMA-remapping hardware.
As part of the secure launch process, the SINIT-AC module verifies the protected
memory regions are properly configured and enabled. Once launched, the MVMM can
setup the initial DMA-remapping structures in protected memory (to ensure they are
protected while being setup) before enabling the DMA-remapping hardware units.
To optimally support platform configurations supporting varying amounts of main
memory, the protected memory region is defined as two non-overlapping regions:
• Protected Low-memory Region: This is defined as the protected memory region
below 4 GB to hold the MVMM code/private data, and the initial DMA-remapping
structures that control DMA to host physical addresses below 4 GB. DMA-
remapping hardware implementations on platforms supporting Intel TXT are
required to support protected low-memory region 5.
• Protected High-memory Region: This is defined as a variable sized protected
memory region above 4 GB, enough to hold the initial DMA-remapping structures
for managing DMA accesses to addresses above 4 GB. DMA-remapping hardware
implementations on platforms supporting Intel TXT are required to support
protected high-memory region 6, if the platform supports main memory above
4GB.