Datasheet
Processor Configuration Registers
210 Datasheet, Volume 2
2.15.26 IEUADDR_REG—Invalidation Event Upper Address
Register
This register specifies the Invalidation Event interrupt message upper address. This
register is treated as reserved by implementations reporting both Queued Invalidation
(QI) and Extended Interrupt Mode (EIM) as not supported in the Extended Capability
register.
2.15.27 IRTA_REG—Interrupt Remapping Table Address Register
Register providing the base address of Interrupt remapping table. This register is
treated as reserved by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: AC–AFh
Reset Value: 00000000h
Access: RW
Bit Attr
Reset
Value
Description
31:0 RW
00000000
h
Message Upper Address (MUA)
Hardware implementations supporting Queued Invalidations and Extended
Interrupt Mode are required to implement this register.
Software requirements for programming this register are described in the
VTd specification. Hardware implementations not supporting Queued
Invalidations and Extended Interrupt Mode may treat this field as reserved.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: B8–BFh
Reset Value: 0000000000000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
63:12 RW
00000000
00000h
Interrupt Remapping Table Address (IRTA)
This field points to the base interrupt remapping table.
Hardware ignores and not 63:HAW, where HAW is the width.
Reads of this field returns last programmed to it.