Datasheet

Processor Configuration Registers
206 Datasheet, Volume 2
2.15.18 PHMLIMIT_REG—Protected High-Memory Limit Register
Register to setup the limit address of DMA protected high-memory region. This register
must be setup before enabling protected memory through PMEN_REG, and must not be
updated when protected memory regions are enabled. When LT.CMD.LOCK.PMRC
command is invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC
command is invoked, this register is unlocked (treated RW). This register is always
treated as RO for implementations not supporting protected high memory region
(PHMR field reported as 0 in the Capability register). The alignment of the protected
high memory region limit depends on the number of reserved bits (N) of this register.
Software may determine the value of N by writing all 1's to this register, and finding
most significant zero bit position below host address width (HAW) in the value read
back from the register. Bits N:0 of the limit register is decoded by hardware as all 1s.
The protected high-memory base and limit registers functions as follows:
• Programming the protected low-memory base and limit registers with the same
value in bits HAW:(N+1) specifies a protected low-memory region of size 2(N+1)
bytes.
• Programming the protected high-memory limit register with a value less than the
protected high-memory base register disables the protected high-memory region.
2.15.19 IQH_REG—Invalidation Queue Head Register
This register indicates the invalidation queue head. This register is treated as reserved
by implementations reporting Queued Invalidation (QI) as not supported in the
Extended Capability register.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 78–7Fh
Reset Value: 0000000000000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
63:21 RW 00000000
000h
Protected High-Memory Limit (PHML)
This register specifies the last host physical address of the DMA protected
high-memory region in system memory. Hardware may not use bits 63:HAW,
where HAW is the host address width.
20:0 RO 000000h Reserved
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 80–87h
Reset Value: 0000000000000000h
Access: RO
Bit Attr
Reset
Value
Description
63:19 RO 00000000
0000h
Reserved
18:4 RO 0000h Queue Head (QH)
This field specifies the offset (128-bit aligned) to the invalidation queue for
the command that will be fetched next by hardware. Hardware resets this
field to 0 whenever the queued invalidation is disabled (QIES field Clear in
the Global Status register).
3:0 RO 0h Reserved