Datasheet

Datasheet, Volume 2 205
Processor Configuration Registers
2.15.17 PHMBASE_REG—Protected High-Memory Base Register
This register is used to setup the base address of DMA protected high-memory region.
This register must be setup before enabling protected memory through PMEN_REG,
and must not be updated when protected memory regions are enabled. When
LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO). When
LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated RW).
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as 0 in the Capability register). The alignment of
the protected high memory region base depends on the number of reserved bits (N) of
this register. Software may determine the value of N by writing all 1s to this register,
and finding most significant zero bit position below host address width (HAW) in the
value read back from the register. Bits N:0 of the limit register is decoded by hardware
as all 0s.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 70–77h
Reset Value: 0000000000000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
63:21 RW
00000000
000h
Protected High-Memory Base (PHMB)
This register specifies the base of size aligned, protected memory region in
system memory. Hardware may not utilize bits 63:HAW, where HAW is the
host address width. The protected high-memory region has a minimum size
of 2 MB and must be size aligned.
20:0 RO 000000h Reserved