Datasheet

Processor Configuration Registers
204 Datasheet, Volume 2
2.15.16 PLMLIMIT_REG—Protected Low-Memory Limit Register
Register to setup the limit address of DMA protected low-memory region. This register
must be setup before enabling protected memory through PMEN_REG, and must not be
updated when protected memory regions are enabled. When LT.CMD.LOCK.PMRC
command is invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC
command is invoked, this register is unlocked (treated RW). This register is always
treated as RO for implementations not supporting protected low memory region (PLMR
field reported as 0 in the Capability register). The alignment of the protected low
memory region limit depends on the number of reserved bits (N) of this register.
Software may determine the value of N by writing all 1s to this register, and finding
most significant zero bit position with 0 in the value read back from the register. Bits
N:0 of the limit register is decoded by hardware as all 1s. The Protected low-memory
base & limit registers functions as follows.
• Programming the protected low-memory base and limit registers with the same
value in bits 31:(N+1) specifies a protected low-memory region of size 2(N+1)
bytes.
• Programming the protected low-memory limit register with a value less than the
protected low-memory base register disables the protected low-memory region.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 6C–6Fh
Reset Value: 00000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
31:21 RW 000h
Protected Low-Memory Limit (PLML)
This register specifies the last host physical address of the DMA protected
low-memory region in system memory.
20:0 RO 000000h Reserved