Datasheet

Processor Configuration Registers
200 Datasheet, Volume 2
2.15.10 FEDATA_REG—Fault Event Data Register
This register specifies the interrupt message data.
2.15.11 FEADDR_REG—Fault Event Address Register
This register specifies the interrupt message address.
2.15.12 FEUADDR_REG—Fault Event Upper Address Register
This register specifies the interrupt message address. For platforms supporting only
interrupt messages in the 32-bit address range, this register is treated as read-only
(0).
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 3C–3Fh
Reset Value: 00000000h
Access: RO, RW
Bit Attr
Reset
Value
Description
31:16 RO 0000h
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit MSI data fields.
Hardware implementations supporting only 16-bit MSI data may treat this
field as read-only (0).
15:0 RW 0000h
Interrupt message data (ID)
Data value in the fault-event interrupt message.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 40–43h
Reset Value: 00000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
31:2 RW 00000000
h
Message Address (MA)
When fault events are enabled, the contents of this register specify the
DWORD aligned address (bits 31:2) for the MSI memory write transaction.
1:0 RO 0h Reserved
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 44–47h
Reset Value: 00000000h
Access: RO
Bit Attr
Reset
Value
Description
31:0 RO
00000000
h
Message upper address (MUA)
This register need to be implemented only if hardware supports 64-bit
message address. If implemented, the contents of this register specify the
upper 32-bits of a 64- bit MSI write transaction.
If hardware does not support 64-bit messages, the register is treated as
read-only (0).